The present invention relates to programmable logic integrated circuits with an embedded processor. More specifically, the present invention relates to input/output (I/O) circuitry that is shared between a processor portion and a programmable logic portion of the integrated circuit.
Previously known integrated circuits (or chips) such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) have provided I/O (input/output) pins that provide external access to circuits on the chip. Certain integrated circuits may require a large number of I/O pins on the chip to provide support to the internal circuitry and to provide the desired functionality and versatility. I/O pins and associated circuitry can take up a significant amount of room on the chip. Furthermore, integrated circuit technology continues to advance, and it is possible and desirable to provide more functionality on an integrated circuit. More I/O pins are generally needed to access or otherwise accommodate the additional on-chip functionality.
As an increasing number of I/O pins are required to be placed on a chip, chips must be made larger to accommodate the additional I/O pins. It may be undesirable to use chips with large surface areas in certain applications in which board space is limited. Also, packages that house chips typically accommodate a fixed number of I/O pins. There may be only a limited number of package sizes (e.g., 100 pins, 250 pins, 500 pins, and so forth). These may be “standard” available package sizes. Therefore, when a chip exceeds the maximum number of I/O pins that a particular package size can accommodate, the chip must be housed in the next larger package size. This can significantly increase the cost of manufacturing the chip.
Therefore, there is a need for circuitry and methods that reduce or limit the number of I/O pins on a programmable logic chip.